The present invention relates to a semiconductor device having a memory device such as an MTJ (Magnetic Tunnel Junction) device and a manufacturing method therefor.
MRAM is a memory that uses a magnetic material for memory devices and stores data by the orientation of magnetization in the magnetic material, that is, holds data by storing information in the spin of electrons. The circuit of the MRAM is randomly accessible. One of memory devices utilized as MRAM is MTJ device. In this specification, MTJ device is used as a concept including TMR (Tunneling Magneto Resistance) device.
FIG. 29 is a sectional view illustrating the general configuration of a memory device in a conventional MRAM. As illustrated in the drawing, an MTJ device MD9 is formed over a metal film strap EB9 that makes a lower electrode and an upper electrode ET9 is formed over the MTJ device MD9. The MTJ device MD9 is formed of a laminated structure obtained by laminating a lower magnetic film 96, a tunnel insulating film 97, and an upper magnetic film 98 in this order.
FIG. 30 is an explanatory drawing illustrating the outline of a conventional MRAM configuration. As illustrated in the drawing, multiple MTJ devices MD9 are arranged in a matrix pattern. (The metal film strap EB9 or the upper electrode ET9 is not shown in the drawing.) Multiple upper Cu wirings Y1 to Y5 are formed along the direction of columns (obliquely horizontal direction in the drawing) and are electrically coupled with MTJ devices MD9 on a column-by-column basis. Multiple lower Cu wirings X1 to X6 are formed along the direction of rows (obliquely vertical direction in the drawing) and are electrically coupled with MTJ devices MD9 on a row-by-row basis.
FIG. 31 is a sectional view illustrating the detailed relation of coupling between an MTJ device MD9 and an upper Cu wiring 37 and lower Cu wirings 25 (read line 25r, digit line (word line) 25d). As illustrated in the drawing, the lower Cu wirings 25 are selectively formed so that they penetrate an interlayer insulating film 23 formed over a semiconductor substrate (not shown). A silicon nitride film 86 and an interlayer insulating film 24 are laminated over the interlayer insulating film 23 including the lower Cu wirings 25. A via hole 109 (local via) is provided in the silicon nitride film 86 and the interlayer insulating film 24 corresponding to part of a formation region for the read line 25r as viewed on a plane. A metal film strap EB9 that makes an extraction wiring (LS (Local Strap)) is selectively formed over the interlayer insulating film 24 and in the bottom face of and over the side face of the via hole 109 and as a result, the metal film strap EB9 is electrically coupled with the read line 25r. 
Over the metal film strap EB9, the MTJ device MD9 is selectively formed in a region corresponding to part of a formation region for the digit line 25d as viewed on a plane. An upper electrode ET9 is formed over the MTJ device MD9.
An interlayer insulating film 66 comprised of SiO2 is formed so that it covers the entire surface including the MTJ device MD9 and the upper electrode ET9.
The upper Cu wiring 37 that makes a bit line is selectively formed over the interlayer insulating film 66. A via hole 49 is formed in part of the region where the MTJ device MD9 is formed as viewed on a plane so that the via hole penetrates the interlayer insulating film 66. The upper Cu wiring 37 is also filled in this via hole 49 and as a result, the upper Cu wiring 37 and the upper electrode ET9 are electrically coupled with each other.
As mentioned above, the metal film strap EB9 is formed in the via hole 109 and the lower Cu wirings 25 (read line 25r) and the MTJ device MD9 are thereby electrically coupled with each other. This common structure of coupling (hereafter, also simply referred to as “via LS coupling structure”) is as illustrated in FIG. 31.
The same MRAM structure as the MRAM illustrated in FIG. 29 to FIG. 31 is disclosed in, for example, Patent Document 1.
To obtain the structure illustrated in FIG. 31, in general, a manufacturing process comprised of the following steps (1) to (9) is carried out. (1) The silicon nitride film 86 and the interlayer insulating film 24 are deposited over the interlayer insulating film 23 including the lower Cu wirings 25. (2) The via hole 109 penetrating the silicon nitride film 86 and the interlayer insulating film 24 is selectively formed. (3) A metal thin film that makes the metal film strap EB9 is deposited over the interlayer insulating film 24 including the via hole 109. (4) Respective formation layers for the MTJ device MD9 and the upper electrode ET9 are deposited over the metal film strap EB9 over the interlayer insulating film 24. (5) The above formation layers are patterned to obtain the MTJ device MD9 and the upper electrode ET9. (6) The metal thin film formed at the above step (3) is patterned to form the metal film strap EB9. (7) The interlayer insulating film 66 is deposited over the entire surface. (8) Formation regions for the via hole 49 penetrating the interlayer insulating film 66 and the upper Cu wiring 37 are selectively formed. (9) The upper Cu wiring 37 is deposited and filled and then CMP processing is carried out.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2005-85821